#include "inc/hw_memmap.h"
#include "adc12_a.h"
#include "SIadc.h"
#include "gpio.h"
#include "main.h"
/*
#define SI_ADC_PORT		GPIO_PORT_P6
#define SI_8_ADC_PIN	GPIO_PIN7		// J2-1, A7
#define SI_7_ADC_PIN	GPIO_PIN6		// J2-2, A6
#define SI_6_ADC_PIN	GPIO_PIN5		// J2-3, A5
#define SI_5_ADC_PIN	GPIO_PIN4		// J2-4, A4
#define SI_4_ADC_PIN	GPIO_PIN3		// J2-5, A3
#define SI_3_ADC_PIN	GPIO_PIN2		// J2-6, A2
#define SI_2_ADC_PIN	GPIO_PIN1		// J2-7, A1
#define SI_1_ADC_PIN	GPIO_PIN0		// J2-8, A0*/
#define SI_ADC_PIN_MASK	(GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7)


#define ADC_12BIT_0p0V_FROM_3p3V	0
#define ADC_12BIT_0p15V_FROM_3p3V	186
#define ADC_12BIT_0p2V_FROM_3p3V	248
#define ADC_12BIT_0p3V_FROM_3p3V	372
#define ADC_12BIT_0p4V_FROM_3p3V	496
#define ADC_12BIT_1p9V_FROM_3p3V	2358
#define ADC_12BIT_2p0V_FROM_3p3V	2482
#define ADC_12BIT_2p1V_FROM_3p3V	2605
#define ADC_12BIT_2p2V_FROM_3p3V	2730

#define SI_FAULT_OUT_OF_RANGE_HIGH		ADC_12BIT_2p2V_FROM_3p3V
#define SI_FAULT_OUT_OF_RANGE_LOW 		ADC_12BIT_0p2V_FROM_3p3V
#define SI_FAULT_OUT_OF_RANGE_MID_LOW	ADC_12BIT_0p4V_FROM_3p3V
#define SI_FAULT_OUT_OF_RANGE_MID_HIGH	ADC_12BIT_1p9V_FROM_3p3V
#define SI_FAULT 						ADC_12BIT_0p3V_FROM_3p3V

#define SI_ALARM						ADC_12BIT_1p9V_FROM_3p3V//ADC_12BIT_2p0V_FROM_3p3V
#define SI_RETURN_TO_NORMAL_FROM_ALARM	ADC_12BIT_2p0V_FROM_3p3V


/*
#define ADC_GPIO_PORT 		GPIO_PORT_P7
#define ADC_GPIO_ADC_A15 	GPIO_PIN7
#define ADC_GPIO_ADC_A12 	GPIO_PIN4
*/

/*
#define ADC_GPIO_PORT2 		GPIO_PORT_P6
#define ADC_GPIO_ADC_A7 	GPIO_PIN7
#define ADC_GPIO_ADC_A6 	GPIO_PIN6
#define ADC_GPIO_ADC_A5 	GPIO_PIN5
#define ADC_GPIO_ADC_A4 	GPIO_PIN4
#define ADC_GPIO_ADC_A3 	GPIO_PIN3
#define ADC_GPIO_ADC_A2 	GPIO_PIN2
#define ADC_GPIO_ADC_A1 	GPIO_PIN1
#define ADC_GPIO_ADC_A0 	GPIO_PIN0
*/

#define SI_1_ADC_GPIO_PIN 	SI_1_ADC_PIN
#define SI_1_ADC_MEM		ADC12_A_MEMORY_0
#define SI_1_ADC_INPUT		ADC12_A_INPUT_A0//ADC12_A_INPUT_A7
#define SI_1_ADC_IE			ADC12IE0
#define SI_1_ADC_EOQ		ADC12_A_NOTENDOFSEQUENCE
//#define SI_1_ALARM_MAX 		2600
//#define SI_1_ALARM_MIN 		500

//#define SI_2_ADC_GPIO_PIN 	SI_2_ADC_PIN
//#define SI_2_ADC_MEM		ADC12_A_MEMORY_1
//#define SI_2_ADC_INPUT		ADC12_A_INPUT_A1//ADC12_A_INPUT_A6
//#define SI_2_ADC_IE			ADC12IE1
//#define SI_2_ADC_EOQ		ADC12_A_NOTENDOFSEQUENCE

#define SI_8_ADC_GPIO_PIN 	SI_8_ADC_PIN
#define SI_8_ADC_MEM		ADC12_A_MEMORY_1
#define SI_8_ADC_INPUT		ADC12_A_INPUT_A7//ADC12_A_INPUT_A6
#define SI_8_ADC_IE			ADC12IE7
#define SI_8_ADC_EOQ		ADC12_A_ENDOFSEQUENCE

#define SI_X_ADC_GPIO_PORT	GPIO_PORT_P6
#define SI_X_ADC_BASE		ADC12_A_BASE
#define SI_X_VREF_POS		ADC12_A_VREFPOS_AVCC
#define SI_X_ADC_VREF_NEG 	ADC12_A_VREFNEG_AVSS

#define SI_X_ADC_START_BASE	SI_X_ADC_BASE//SI_1_ADC_BASE
#define SI_X_ADC_STOP_BASE	SI_X_ADC_BASE//SI_8_ADC_BASE
#define SI_X_ADC_START_MEM	SI_1_ADC_MEM
#define SI_X_ADC_STOP_IE	SI_8_ADC_IE
#define SI_X_ADC_TYPE		ADC12_A_SEQOFCHANNELS//ADC12_A_REPEATED_SEQOFCHANNELS

static unsigned char adcTurn = 0;
static unsigned int adcArray[NUMBER_ADC_READINGS];

void SIadc_adc12_init_repeated(void)
{
	//Enable A/D channel inputs
	GPIO_setAsPeripheralModuleFunctionInputPin(SI_X_ADC_GPIO_PORT, SI_ADC_PIN_MASK);

	//Initialize the ADC12_A Module
	/*
	 * Base address of ADC12_A Module
	 * Use internal ADC12_A bit as sample/hold signal to start conversion
	 * USE MODOSC 5MHZ Digital Oscillator as clock source
	 * Use clock divider of 32
	 */
	ADC12_A_init(ADC12_A_BASE, ADC12_A_SAMPLEHOLDSOURCE_SC, ADC12_A_CLOCKSOURCE_ADC12OSC, ADC12_A_CLOCKDIVIDER_32);

	ADC12_A_enable(ADC12_A_BASE);

	/*
	 * Base address of ADC12_A Module
	 * For memory buffers 0-7 sample/hold for 16 clock cycles
	 * For memory buffers 8-15 sample/hold for 4 clock cycles (default)
	 * Enable Multiple Sampling
	 */
	ADC12_A_setupSamplingTimer(ADC12_A_BASE, ADC12_A_CYCLEHOLD_8_CYCLES, ADC12_A_CYCLEHOLD_8_CYCLES, ADC12_A_MULTIPLESAMPLESENABLE);

	//Configure Memory Buffers
	/*
	 * Base address of the ADC12_A Module
	 * Configure memory buffer 0
	 * Map input A8 to memory buffer 0
	 * Vref+ = AVcc
	 * Vref- = AVss
	 * Memory buffer 0 is not the end of a sequence
	 */
	int i;
	unsigned char endOfSeq = SI_1_ADC_EOQ;
	for (i=0; i<8; i++)
	{
		if (i==7) endOfSeq = SI_8_ADC_EOQ;
		ADC12_A_memoryConfigure(SI_X_ADC_BASE, SI_1_ADC_MEM+i, SI_1_ADC_INPUT+i, SI_X_VREF_POS, SI_X_ADC_VREF_NEG, endOfSeq);
	}
//	ADC12_A_memoryConfigure(SI_X_ADC_BASE, SI_1_ADC_MEM, SI_1_ADC_INPUT, SI_X_VREF_POS, SI_X_ADC_VREF_NEG, SI_1_ADC_EOQ);
//	ADC12_A_memoryConfigure(SI_X_ADC_BASE, SI_2_ADC_MEM, SI_2_ADC_INPUT, SI_X_VREF_POS, SI_X_ADC_VREF_NEG, SI_2_ADC_EOQ);

	//Enable memory buffer 1 interrupt
	ADC12_A_enableInterrupt(SI_X_ADC_STOP_BASE, SI_X_ADC_STOP_IE);

	//Enable/Start first sampling and conversion cycle
	/*
	 * Base address of ADC12_A Module
	 * Start the conversion into memory buffer 0
	 * Use the repeated sequence of channels
	 */
	ADC12_A_startConversion(SI_X_ADC_START_BASE, SI_X_ADC_START_MEM, SI_X_ADC_TYPE);

}
void SIadc_adc12_init_sequence(void)
{
	//Enable A/D channel inputs
	GPIO_setAsPeripheralModuleFunctionInputPin(SI_X_ADC_GPIO_PORT, SI_ADC_PIN_MASK);

	//Initialize the ADC12_A Module
	/*
	 * Base address of ADC12_A Module
	 * Use internal ADC12_A bit as sample/hold signal to start conversion
	 * USE MODOSC 5MHZ Digital Oscillator as clock source
	 * Use clock divider of 32
	 */
	ADC12_A_init(ADC12_A_BASE, ADC12_A_SAMPLEHOLDSOURCE_SC, ADC12_A_CLOCKSOURCE_ADC12OSC, ADC12_A_CLOCKDIVIDER_32);

	ADC12_A_enable(ADC12_A_BASE);

	/*
	 * Base address of ADC12_A Module
	 * For memory buffers 0-7 sample/hold for 16 clock cycles
	 * For memory buffers 8-15 sample/hold for 4 clock cycles (default)
	 * Enable Multiple Sampling
	 */
	ADC12_A_setupSamplingTimer(ADC12_A_BASE, ADC12_A_CYCLEHOLD_4_CYCLES, ADC12_A_CYCLEHOLD_4_CYCLES, ADC12_A_MULTIPLESAMPLESENABLE);
//	ADC12_A_setupSamplingTimer(ADC12_A_BASE, ADC12_A_CYCLEHOLD_32_CYCLES, ADC12_A_CYCLEHOLD_4_CYCLES, ADC12_A_MULTIPLESAMPLESENABLE);

	//Configure Memory Buffers
	/*
	 * Base address of the ADC12_A Module
	 * Configure memory buffer 0
	 * Map input A8 to memory buffer 0
	 * Vref+ = AVcc
	 * Vref- = AVss
	 * Memory buffer 0 is not the end of a sequence
	 */
	int i;
	unsigned char endOfSeq = SI_1_ADC_EOQ;
	for (i=0; i<8; i++)
	{
		if (i==7) endOfSeq = SI_8_ADC_EOQ;
		ADC12_A_memoryConfigure(SI_X_ADC_BASE, SI_1_ADC_MEM+i, SI_1_ADC_INPUT+i, SI_X_VREF_POS, SI_X_ADC_VREF_NEG, endOfSeq);
	}
//	ADC12_A_memoryConfigure(SI_X_ADC_BASE, SI_1_ADC_MEM, SI_1_ADC_INPUT, SI_X_VREF_POS, SI_X_ADC_VREF_NEG, SI_1_ADC_EOQ);
//	ADC12_A_memoryConfigure(SI_X_ADC_BASE, SI_2_ADC_MEM, SI_2_ADC_INPUT, SI_X_VREF_POS, SI_X_ADC_VREF_NEG, SI_2_ADC_EOQ);

	//Enable memory buffer 1 interrupt
	ADC12_A_enableInterrupt(SI_X_ADC_STOP_BASE, SI_X_ADC_STOP_IE);
}
void SIadc_startADCsampleCycle(void)
{
	//Enable/Start first sampling and conversion cycle
	/*
	 * Base address of ADC12_A Module
	 * Start the conversion into memory buffer 0
	 * Use the repeated sequence of channels
	 */
	ADC12_A_startConversion(SI_X_ADC_START_BASE, SI_X_ADC_START_MEM, SI_X_ADC_TYPE);

}
void SIadc_disableInterrupts(void)
{
	ADC12_A_disableInterrupt(SI_X_ADC_STOP_BASE, SI_X_ADC_STOP_IE);
}
void SIadc_enableInterrupts(void)
{
	ADC12_A_enableInterrupt(SI_X_ADC_STOP_BASE, SI_X_ADC_STOP_IE);
}
void SIadc_testIncrmentAdcTurn(void)
{
	adcTurn++;
}
unsigned char SIadc_getAdcTurn(void)
{
	unsigned char rtn;
//	_disable_interrupt();
	rtn = adcTurn;
//	__bis_SR_register(GIE);
	return rtn;
}
int SIadc_getReading(unsigned char index, unsigned int * adcValue)
{
	if (index > NUMBER_ADC_READINGS) {
		return -1;
	}
	*adcValue = adcArray[index];
	return 0;
}
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
{
//	P8OUT &= ~(1<<4);
//	P8OUT |= 1<<0;
	test_testPin2_Off();
	test_testPin4_On();
	adcTurn++;// = (turn+1)%2;
//	Buzzer_on();
//	if (turn%2)
//		SI_TestADport_On();
//	else
//		SI_TestADport_Off();
	unsigned int i;
    switch (__even_in_range(ADC12IV,34)){
        case  0: break;   //Vector  0:  No interrupt
        case  2: break;   //Vector  2:  ADC overflow
        case  4: break;   //Vector  4:  ADC timing overflow
        case  6: break;   //Vector  6:  ADC12IFG0
        case  8: break;   	  //Vector  8:  ADC12IFG1
        case  10: break;   	  //Vector  10:  ADC12IFG2
        case  12: break;   	  //Vector  12:  ADC12IFG3
        case  14: break;   	  //Vector  14:  ADC12IFG4
        case  16: break;   	  //Vector  16:  ADC12IFG5
        case  18: break;   	  //Vector  18:  ADC12IFG6
        case  20:    	  //Vector  20:  ADC12IFG7

			//Move A0 results, IFG is cleared
 //       	SI_1_adc_counts = ADC12_A_getResults(SI_X_ADC_BASE, SI_1_ADC_MEM + 0);

			//Move A1 results, IFG is cleared
 //       	SI_2_adc_counts = ADC12_A_getResults(SI_X_ADC_BASE, SI_1_ADC_MEM + 1);

//        	unsigned int adcValue;
//        	unsigned int *adcCount = &SI_2_adc_counts;

        	for (i=0; i<NUMBER_ADC_READINGS; i++)
        	{
        		adcArray[i] = ADC12_A_getResults(SI_X_ADC_BASE, i);
 //       		SI_threadInfo[i].adcCount = ADC12_A_getResults(SI_X_ADC_BASE, i);
 //       		adcValue = ADC12_A_getResults(SI_X_ADC_BASE, i);
   //     		*adcCount = ADC12_A_getResults(SI_X_ADC_BASE, i);
        		__no_operation();
        	}
//        	ADC12_A_clearInterrupt(SI_X_ADC_BASE, 0xFFFF);
//        	Buzzer_off();
        	test_testPin4_Off();
        	ADC12IFG &= ~0xFF;
			break;
        case 22: break;   //Vector 22:  ADC12IFG8
        case 24: break;   //Vector 24:  ADC12IFG9
        case 26: break;   //Vector 26:  ADC12IFG10
        case 28: break;   //Vector 28:  ADC12IFG11
        case 30: break;   //Vector 30:  ADC12IFG12
        case 32: break;   //Vector 32:  ADC12IFG13
        case 34: break;   //Vector 34:  ADC12IFG14
        default: break;
    }
}



